CAP1I=DISABLED_, CAP0I=DISABLED_, CAP0RE=DISABLED_, CAP1RE=DISABLED_, CAP1FE=DISABLED_, CAP0FE=DISABLED_
Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.
| CAP0RE | Capture on CT32B0_CAP0 rising edge: a sequence of 0 then 1 on CT32B0_CAP0 will cause CR0 to be loaded with the contents of TC. 0 (DISABLED_): Disabled. 1 (ENABLED_): Enabled. |
| CAP0FE | Capture on CT32B0_CAP0 falling edge: a sequence of 1 then 0 on CT32B0_CAP0 will cause CR0 to be loaded with the contents of TC. 0 (DISABLED_): Disabled. 1 (ENABLED_): Enabled. |
| CAP0I | Interrupt on CT32B0_CAP0 event: a CR0 load due to a CT32B0_CAP0 event will generate an interrupt. 0 (DISABLED_): Disabled. 1 (ENABLED_): Enabled. |
| RESERVED | Reserved. |
| CAP1RE | Capture on CT32B0_CAP1 rising edge: a sequence of 0 then 1 on CT32B0_CAP1 will cause CR1 to be loaded with the contents of TC. 0 (DISABLED_): Disabled. 1 (ENABLED_): Enabled. |
| CAP1FE | Capture on CT32B0_CAP1 falling edge: a sequence of 1 then 0 on CT32B0_CAP1 will cause CR1 to be loaded with the contents of TC. 0 (DISABLED_): Disabled. 1 (ENABLED_): Enabled. |
| CAP1I | Interrupt on CT32B0_CAP1 event: a CR1 load due to a CT32B0_CAP1 event will generate an interrupt. 0 (DISABLED_): Disabled. 1 (ENABLED_): Enabled. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |